View FDMF6707B_9071024.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2011 semiconductor components industries, llc. publication order number: december - 2017, rev. 2 fdmf670 7b /d fdmf670 7b - extra - small high - performance, high - frequency drmos module fdmf670 7b - ex tra - small, high - performance, high - frequency drmos module benefits ? ultr a - compact 6x 6mm pqfn, 72 % space - s aving c ompared to c onventional d iscrete s olutions ? fu lly o ptimized s ystem e f f iciency ? clean sw itching w aveform s w ith m inimal ri nging ? high - c urrent h andling features ? over 93% peak - e f f iciency ? high - c urrent h andling of 50 a ? high - performance pqfn copper - clip package ? 3 - s tate 3.3 v pwm i nput d river ? skip - m ode smod# ( low - s ide g ate t urn o ff) i nput ? thermal w arning f lag for over - t emperature c ondition ? dr i ver o utp ut d isable f unction (disb# p in) ? internal p ull - u p and p ul l - d ow n f or smod # and disb# i nput s , r espectively ? on semiconductor pow ertrench? t echnology mosfets f or c lean v oltag e w aveforms and r educed r inging ? on semiconductor syncfet ? ( i ntegrated schottky d iode) t e chnol ogy in the low - s ide mosfet ? inte grated b ootstrap schottky d iode ? adaptive g ate d rive t imi ng for s hoot - t hrough p rotection ? under - v ol tage l ockout (uvlo) ? optimized for s wi tching fr equencies up to 1 m h z ? low - p rof ile smd p ackage ? on semiconductor green packaging and rohs c ompliant ? based o n the intel ? 4.0 drmos standard description the xs ? drmos f a mily is on semiconductor ?s next - generation, fully optimized, ultra - compact, integrated mosfet plus driver pow er stage solution for high - current, high - frequency , synchronous buck dc - dc applications. the fdmf 6707b integrates a driver ic, tw o pow er mosfets , and a bootstrap schottky diode into a thermally enhance d, ultra - compact 6x 6 mm pq f n package. with an integrated approach, the complete sw itching pow er stage is optimized for driver and mosfet dynamic performance, system inductance, and p ow er mosfet r ds(o n) . xs ? dr mo s uses o n semiconductor 's hig h - performance pow ertrench ? mosfet technology, w hich dramatically reduces sw itch ringing, eliminating the snubber circuit in most buck converter applications . a new driver ic w ith reduced dead times and propagation delays furthe r enhances performance. a ther mal w arning function w ar n s of potential over - te mperature situation s . fdmf670 7b also incorporates features such as skip mode ( smod ) for im proved light - load efficiency , along w ith a 3 - state 3.3 v pwm input for compatibility w ith a w ide range of pwm controll ers. applications ? high - performance gaming motherboards ? compact blade servers , v - core and non - v - core dc- dc converters ? d esktop computers, v - core and non - v - cor e dc- dc converters ? workstations ? high - c urrent dc - dc point - of - load (pol ) c onverters ? netw orking and t elecom m icroprocessor v oltage r egulators ? small form - f actor voltage r egulator m odules ordering information part number current rating package top mark fdmf670 7b 5 0 a 40- lead, clipbond pqfn drmos, 6.0 mm x 6.0 mm package fdmf67 0 7b
www.onsemi.com 2 fdmf670 7b - extra - small high - performance, high - frequency drmos module typical application circuit v 5 v disb pwm input off on c vdrv c vin c boot r boot l out c out v in fdmf 6707 b open - drain output vdrv vcin vin pwm thwn # boot cgnd pgnd disb # phase smod # c vcin v out vswh 3 v ~ 15 v r vcin figure 1. typical application circuit drmos block diagram figure 2. dr m os blo ck diag r am smod# pwm vcin vdrv vin pgnd phase gh d boot boot gl cgnd disb# th w n# q1 hs power mosfet input 3 - state logic r up_pwm v ci n v ci n uvlo gh logic lev el shift dea d - t ime control temp. sense 30k ? ? gl logic 10a 10a r dn_pw m q2 ls power mosfet vswh v drv
www.onsemi.com 3 fdmf670 7b - extra - small high - performance, high - frequency drmos module pin configuration 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 20 19 18 17 16 15 14 13 12 11 vswh 43 vin 42 cgnd 41 smod# vcin vdrv boot cgnd gh phase nc vin vin vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd vswh vswh pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pwm disb# thwn cgnd gl vswh vswh vswh vswh vswh 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 20 19 18 17 16 15 14 13 12 11 vswh 43 vin 42 cgnd 41 smod# vcin vdrv boot cgnd gh phase nc vin vin vin vin vin vin vswh pgnd pgnd pgnd pgnd pgnd vswh vswh pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pwm disb# thwn cgnd gl vswh vswh vswh vswh vswh figure 3. bottom view figure 4. top view p in definitions pin # name description 1 smod# when smod# = hi gh , the low - side driver is the inverse of pwm input. when smod# = l o w , the low - side dri ver is disabled. this pin has a 10 a interna l pull - up current source . do not add a noise filter cap acitor . 2 v cin ic b ias s upply. minimum 1 f ceramic capacitor is recommended from this pin to cgnd. 3 v drv pow er for g ate d r iv er . minimum 1 f ceramic capacitor is recommended connected as close as p ossible from this pin to cgnd. 4 boot bootstrap s upply i nput. provides voltage supply to the high - side mosfet driver. connect a bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ic g round. ground return for driver ic. 6 gh for manufactu ring tes t only. this pin must float . it m ust not be connected to any pin. 7 pha se sw itch n ode pin for bootstrap capacitor routing. electrically shorted to vswh pin. 8 nc no c onnect. the pin is not electrically connected internally, but can be connected to vin fo r convenience. 9 - 14, 42 v in pow er i nput. output stage supply voltage. 15, 29 - 35, 43 vswh sw itch n ode i nput. provides return for high - side bootstrapped driver and acts as a sense point for the adapt ive shoot - through protection. 16 ? 28 pgnd pow er g ro und. output stage ground. source pin of the low - side mosfet . 36 gl for manufacturing test only. this pin must float . it m ust not be connected to any pin. 38 thw n # thermal w arning f lag, o pen c ollector o utput. when temperature exceeds the trip limit , the o utput is pulled low . thwn # does n ot disable the module. 39 disb# output d isable. when low , this pin disable s the p ow er mos fet sw itching (gh and gl are held low ). this pin has a 10 a internal pull - dow n current source . do not add a noise filter capacitor . 40 pwm pwm s ignal i nput. this pin accepts a 3 - state 3.3 v pwm signal from the controller.
www.onsemi.com 4 fdmf670 7b - extra - small high - performance, high - frequency drmos module absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended op erating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbo l parameter min. max. unit v cin, v drv , disb#, pwm, smod#, gl, thwn # to cgnd pin s - 0.3 6 .0 v v in to pgnd, cgnd pin s - 0.3 25 .0 boot, gh to v swh, pha se pin s - 0.3 6 .0 boot , pha se , gh to cgnd pins - 0.3 25 .0 vswh to cgnd/ pg nd ( dc o nly) - 0.3 25 .0 v swh to pgnd ( < 20 ns) - 8 .0 25 .0 boot to v drv 22 .0 i thwn# thwn # sink current - 0.1 7 .0 ma i o(av ) ( error! reference source not found. ) v in =12 v, v o =1.0v f sw =3 0 0 khz 50 a f sw =1 mhz 4 5 no t e : 1. i o(av) is rated using o n semiconductor ?s drmos evaluation board, at t a = 25c , w ith natural convection cooling . this rating is limited by the peak drmos temperature, t j = 150c, and varies depending on operating conditi ons and pc b layout . this rating can be changed w ith different application settings . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet spec ifications. o n semiconductor does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v cin control circuit supply voltage 4.5 5 .0 5.5 v v drv gate drive circuit supply voltage 4.5 5 .0 5.5 v v in output stage supply voltage ( 2 ) 3 .0 12 .0 15.0 v no t e : 2. operating at high v in can create excessive ac overshoots on the vswh - to - gnd and boot - to - gnd nodes during mosfet sw itching transients. for reliable drmos operation, vswh - to - gnd and boot - to - gnd mus t remain at or below the absolute maximum ratings show n in the table above . refer to the ? application information ? and ? pcb layout guidelines ? sections of this datasheet for additional information .
www.onsemi.com 5 fdmf670 7b - extra - small high - performance, high - frequency drmos module electrical characteristics typical values are v in = 12 v, v cin = 5 v, v drv = 5 v, and t a = +25c unless otherw ise noted. symbol parameter condition min. typ. max. unit basic operation i q quiescent current i q =i vcin +i vdrv , pwm=l o w or hi gh or float 2 ma uv lo uvlo threshold v cin r ising 2.9 3.1 3.3 v uv lo _h ys t uvlo hysteresis 0.4 v pwm input (vcin = vdrv = 5 v +/ - 10%) r up_pwm pu ll - up impedance 2 6 k k v ih_pwm pwm high level voltage 1.88 2.2 5 2. 6 1 v v tri_hi 3 - state upper threshold 1. 84 2. 20 2. 5 6 v v tri_lo 3 - state low er threshold 0. 70 0.9 5 1.1 9 v v il_pwm pwm low level voltage 0. 62 0 . 8 5 1 .13 v t d_hold - off 3 - s tate shutoff time 160 200 ns v hiz_pwm 3 - s tate open voltage 1.4 0 1.6 0 1.9 0 v pwm input (vcin = vdrv = 5 v 5 %) r up_pwm pu ll - up impedance 2 6 k k v ih_pwm pwm high level voltage 2. 0 0 2.2 5 2. 50 v v tri_hi 3 - sta te upper threshold 1.94 2. 2 0 2. 46 v v tri_lo 3 - state low er threshold 0. 75 0.9 5 1. 1 5 v v il_pwm pwm low level voltage 0. 66 0 . 8 5 1.0 9 v t d_hold - off 3 - state shutoff time 160 200 ns v hiz_pwm 3 - state open voltage 1.4 5 1.6 0 1.8 0 v disb# input v ih_disb high - level input voltage 2 v v il_disb low - level input voltage 0.8 v i pld pu ll - dow n current 10 a t pd_disbl propagation delay pwm=gnd, delay betw een disb# from high to low to gl from high to low 25 ns t pd_disbh propagation delay pwm=g n d, d elay betw een disb# from low to high to gl from low to high 25 ns smod# input v ih_smod high - level input voltage 2 v v il_smod low - level input voltage 0.8 v i pl u pu ll - up current 10 a t pd_slgll propagation delay pwm=gnd, delay betw een smod# f r om high to low to gl from high to low 10 ns t pd_shglh propagation delay pwm=gnd, delay betw een smod# from low to high to gl from low to high 10 n s continued on the following page ?
www.onsemi.com 6 fdmf670 7b - extra - small high - performance, high - frequency drmos module electrical characteristics typical values are v in = 12 v, v cin = 5 v, v drv = 5 v, and t a = +25c unless otherw ise noted. symbol parameter condition min. typ. max. unit thermal warning flag t act activation temperature 150 c t rst reset temperature 135 c r thwn pu ll - dow n resistance i pld =5 ma 30 250ns timeout circuit t d_timeout timeout delay sw=0 v, delay betw een gh from high to low and gl from low to high 250 ns hig h - side driver r source_gh output impedance, sourci ng source current=100 ma 1 r sink_gh output impedance, sinking sink current=100 ma 0.8 n f 6 ns t f_gh fall time gh = 90% to 10%, c load =1.1 nf 5 ns t d_deadon ls to hs deadband time gl g oing low to gh goin g high, 1 v gl to 10 % gh 10 ns t pd_plghl pwm low propagation delay pwm g oing low to gh g oing low, v il_pwm to 90% gh 16 30 ns t pd_phghh pwm high propagation delay (smod # held low) pwm g oing high to gh g oing high, v ih_pwm to 10% gh (smod # =low) 30 ns t pd_tsghh exiting 3 - state propagation delay pwm ( f r om 3 - state) g oing high to gh g oing high, v ih_pwm to 10% gh 30 ns low - side driver r source_gl output impedance, sourcing source current=100 ma 1 ma 0.5 t r_gl rise time gl = 10% to 90%, c load =5.9 nf 2 0 ns t f_gl fall time gl = 90% to 10%, c load =5.9 nf 13 ns t d_deadoff hs to ls deadband time sw going low to gl g oing high, 2.2 v sw to 10% g l 12 ns t pd_phgll pwm - high propagation d elay pwm going high to gl g oing low, v ih_pwm to 90% gl 9 25 ns t pd_tsglh exiting 3 - state propagation delay pwm ( f r om 3 - state) going low to gl g oing high, v il_pwm to 10% gl 20 ns boot diode v f forw ard - voltag e drop i f =10 ma 0.35 v v r breakdow n voltage i r =1 ma 22 v
www.onsemi.com 7 fdmf670 7b - extra - small high - performance, high - frequency drmos module timing diagram figure 5. pwm timing diagram t d_deadon pwm v sw h gh to v sw h gl t pd_phgll t d_deadoff v ih_pwm v il_pwm 90% 90% 1 .0v 10% t pd_plghl 2.2v 10% t d_timeout ( 250ns timeout) 1. 2v
www.onsemi.com 8 fdmf670 7b - extra - small high - performance, high - frequency drmos module ty pical performance characteristics test conditions : v in = 12 v, v out = 1.0 v, v cin = 5 v, v drv = 5 v, l out = 320 nh, t a = 25c, and natural convection cooling, unless otherw ise specified. 0 5 10 15 20 25 30 35 40 45 50 55 0 25 50 75 100 125 150 module output current, i out (a) pcb temperature ( c) f sw = 300khz f sw = 1mhz v in = 12v, v out = 1.0v jpcb = 3.5 c/w 0 1 2 3 4 5 6 7 8 9 10 11 0 5 10 15 20 25 30 35 40 45 module power loss (w) module output current, i out (a) 300khz 500khz 800khz 1mhz figure 6. safe operating area figure 7. module pow er loss vs. output current 0.9 1 1.1 1.2 1.3 1.4 1.5 200 300 400 500 600 700 800 900 1000 normalized module power loss module switching frequency, f sw (khz) i out = 30a 0.9 1.0 1.1 1.2 1.3 4 6 8 10 12 14 16 normalized module power loss module input voltage, v in (v) i out = 30a, f sw = 300khz figure 8. pow er loss vs. sw itching frequency figure 9. pow er loss vs. input voltage 0.90 0.95 1.00 1.05 1.10 4.50 4.75 5.00 5.25 5.50 normalized module power loss driver supply voltage, v drv and v cin (v) i out = 30a, f sw = 300khz 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 normalized module power loss output voltage, v out (v) i out = 30a, f sw = 300khz figure 10. pow er loss vs. driver supply voltage figure 11. pow er loss vs. output vo ltage
www.onsemi.com 9 fdmf670 7b - extra - small high - performance, high - frequency drmos module typical performance characteristics (continued) test conditions : v in =12 v, v out =1.0 v, v c in =5 v, v drv =5 v, l ou t =320 nh, t a =2 5 c, and natural convection cooling, unless otherw ise specified. 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 225 275 325 375 425 normalized module power loss output inductance, l out (nh) i out = 30a, f sw = 300khz 5 10 15 20 25 30 35 40 45 50 200 300 400 500 600 700 800 900 1000 driver supply current, i vdrv + i vcin (ma) module switching frequency, f sw (khz) i out = 0a figure 12. pow er loss vs. output inductance figure 13. driver supply cur rent vs. frequency 12 13 14 15 16 17 4.50 4.75 5.00 5.25 5.50 driver supply current , i vdrv + i vcin (ma) driver supply voltage, v drv and v cin (v) i out = 0a, f sw = 300khz 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 0 5 10 15 20 25 30 35 40 45 normalized driver supply current module output current, i out (a) 300khz 1mhz figure 14. driver supply current vs. driver supply voltage figure 15. driver supply current vs. output current 0.0 0.5 1.0 1.5 2.0 2.5 3.0 4.50 4.75 5.00 5.25 5.50 pwm threshold voltage (v) driver supply voltage, v cin (v) v ih_pwm v hiz_pwm v tri_hi v t ri_lo v il_pwm t a = 25 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 - 50 - 25 0 25 50 75 100 125 150 pwm threshold voltage (v) driver ic junction temperature, t j ( o c) v cin = 5v v il_pwm v ih_pwm v tri_hi v t ri_lo figure 16. pwm thresholds vs. driver supply voltage figure 17. pwm thresholds vs. temperature
www.onsemi.com 10 fdmf670 7b - extra - small high - performance, high - frequency drmos module typical performance characteristics (continued) test conditi ons : v in =12 v, v out =1.0 v, v c in =5 v, v drv =5 v, l ou t =320 nh, t a =2 5 c, and natural convection cooling, unless otherw ise specified. 1.2 1.4 1.6 1.8 2.0 2.2 4.50 4.75 5.00 5.25 5.50 smod# threshold voltage (v) driver supply voltage, v cin (v) v ih_smod v il_smod t a = 25 c 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 - 50 - 25 0 25 50 75 100 125 150 smod threshold voltage (v) driver ic junction temperature ( o c) v ih_smod v cin = 5v v il_smod figure 18. smod# thresholds vs. driver supply voltage figure 19. smod# thresholds vs. temperature - 12.0 - 11.5 - 11.0 - 10.5 - 10.0 - 9.5 - 9.0 - 50 - 25 0 25 50 75 100 125 150 smod# pull - up current, i plu (ua) driver ic junction temperature, t j ( o c) v cin = 5v 1.40 1.50 1.60 1.70 1.80 1.90 2.00 - 50 - 25 0 25 50 75 100 125 150 disb threshold voltage (v) driver ic junction temperature, t j ( c) v ih_disb v il_disb v cin = 5v figure 20. sm od# pull - up c urrent vs. temperature figure 21. d isable thresholds vs. driver supply voltage 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 4.50 4.75 5.00 5.25 5.50 disb# threshold voltage (v) driver supply voltage, v cin (v) v ih_disb t a = 25 o c v il_disb figure 22. disable thresholds vs. temperature figure 23. disable pull - d ow n c urrent vs. temperature 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 - 50 - 25 0 25 50 75 100 125 150 disb # pull - down current , i p ld ( a) driver ic junction temperature ( o c) v ci = 5v
www.onsemi.com 11 fdmf670 7b - extra - small high - performance, high - frequency drmos module functional description the fdmf 6707b is a driver - plus - fet module optimized for the synchronou s buck converter topology. a single pwm input signal is all that is required to properly drive the high - side and the low - side mosfets. each part is capable of driving speeds up to 1 mhz . vcin and disable (disb#) the vcin pin is monitored by an under - voltag e loc kout ( uv lo) circuit . when v ci n rises above ~3. 1 v, the dr iver is enabled for operation. when v c in falls below ~2. 7 v, the driver is disabled (gh, gl = 0). the driver can also be disabled by pulling the disb# pin l ow ( d is b# < v il_disb ), w hich holds both gl and gh low regardless of the pwm input state. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_disb ). table 1. uvlo and disable logic uv l o disb# driver state 0 x disabled (g h , gl = 0 ) 1 0 disabled (g h , gl = 0 ) 1 1 enabled ( see table 2 ) 1 open disabled (g h , gl = 0 ) no t e : 3. disb# internal pull - dow n current source is 10 a. the rmal warning flag (thwn#) the fdmf 6707b provides a ther mal w arning flag ( t hw n # ) to advi s e of over - temperature condition s. the ther mal w arning flag uses an open - drain output that pull s to cgnd w hen the activation temperature (150c) is reached. the thwn # output return s to high - impedance state once the temperature falls to the reset temperature (135c). for use, t he thwn # ou tput requires a pu ll - up resistor, w hich can be connected to v cin. thwn # does not disable the drmos module. figure 24. t hwn o peration 3 - s tate pwm input the fdmf 6707b incorporates a 3 - state 3.3 v pwm input gate drive design. the 3 - state gate dr ive has both log ic high level and l ow leve l , along w ith a 3 - state shutdow n w indow . when the pwm input signal enters and remains w ithin the 3 - state w indow for a defined hold - off time (t d_hold - of f ), both gl and gh are pulled low . th is feature enables the gate drive to shut dow n both high - and low - s ide mosfets to support features such as phase shedding, a common feature on multi - phase voltage regulators. e xiting 3 - s tate c ondition when exiting a valid 3 - state condition, the fdmf 6707b design follow s the pw m input command. if the pwm input goes from 3 - state to low , the low - side mosfet is turned on. i f the pwm input goes from 3 - state to high , the high - side mosfet is turned on , as illustrated in figure 25 . the fdmf 6707b des ign allo w s for short propagation delays w hen exiting the 3 - state w indow ( see electrical c haracteristics ). low - side driver the low - side driver (gl ) is designed to drive a ground - referenced low r ds(on) n - c hannel mosfet. the bias for gl is internally connected betw e en vdrv and cgnd. when the dr iver is enabled, the driver's output is 180 out of phase w ith the pwm input. when the dr iver is disabled (disb# = 0 v), gl is held low . high - side driver the high - side driv er is des igned to dr ive a floating n - c hannel mosfet. the bias voltage for the high - side driver is dev eloped by a bootstrap supply circuit consisting of the internal schottky diode and external bootstr ap capac itor ( c boot ). dur ing start up, v swh is held at pgnd, allow ing c boot to charge to v drv through the internal diode. when the pwm input goes high , gh begin s to charge the gate of the high - side mosfet ( q1). during this transition, the charge is removed from c boot and deliver ed to the gate of q1. as q1 turns on, v swh rises to v in , forcing the boot pin to v in + v boo t , w hich provide s suf f icien t v gs enhancement for q1. to complete the sw itching cycle, q1 is tur ned off by pulling gh to v swh . c boot is then recharged to v drv w hen v swh falls to pgnd. gh output is in - phase w ith the pwm input. the high - side gate is held l ow w hen the dr iver is disabled or the pwm s ig na l is h eld w ith in th e 3 - state w indow for longer than the 3 - state hold - off time, t d_hold - off . 1 5 0 c activation temperature t j_driver ic ther mal warning nor mal operation h igh l ow 1 3 5c reset temperature thwn # logic state
www.onsemi.com 12 fdmf670 7b - extra - small high - performance, high - frequency drmos module adaptive gate drive circuit the driver ic design ensures minimum mosfet dead time w hi le eliminating potential shoot - t hrough (cross - conduction) currents. it senses the state of the mosfets and adjusts the gate drive adaptively to prevent simultaneous conduct ion . figure 25 provides the relevant timing w aveforms. to prevent overlap during the lo w - to - high sw itching transition (q2 off to q1 on ), the adaptive circuitry monitors the voltage at the gl pin. when t he pwm signal goes high, q2 begin s to turn off af ter a propagation delay (t pd_phgll ). once the gl pin is discharged below ~ 1 v, q1 begins to turn on after adaptive delay t d_deadon . to pre vent overlap dur ing the high - to - low transition (q1 off to q2 on ), the adaptive c ircuitry monitors the voltage at the vswh pin. when the pwm signal goes low, q1 b eg in s to turn off after a propagation delay (t p d_plghl ). once the vswh pin falls below ~2.2 v , q2 begins to turn on after adaptive delay t d_deadoff . additionally, v gs(q1) is monitored. when v gs(q1) is discharged below ~1.2 v, a secondary adaptive delay is init iat ed that results in q2 being dr iven on af ter t d_timeout , regardless of v sw h state. this function is implemented to ensure c boot is recharged each sw itching cycle in the event that the v sw h voltage does not fall below the 2.2 v adaptive threshold. secondary delay t d_timeout is longer than t d_deado ff . figure 25. pwm and 3 - statetiming diagram notes : t p d_xxx = propagation delay from external signal ( pwm, smod# , etc.) to ic generated signal. example ( t pd_phgll C pwm goi ng hi g h to ls v gs (gl) g oi ng low ) t d_xxx = delay from ic generated signal to ic generated signal. example ( t d_deadon C ls v gs ( gl) low to hs v gs (gh) high ) pwm exiting 3 - state t pd_phgll = pwm rise to ls v gs f a l l, v ih_p w m to 90% ls v gs t p d_tsghh = pwm 3 - state to high to hs v gs r i s e, v ih_p w m to 10% hs v gs t pd_plghl = pwm fall to hs v gs f a l l, v il_p w m to 90% hs v gs t p d_tsglh = pwm 3 - state to low to ls v gs rise, v il_p w m to 10% ls v gs t pd_phghh = p wm rise to hs v gs rise, v ih_p w m to 10% hs v gs ( s mod # held low ) smod# dead times t pd_ s lgll = smod# fall to ls v gs fall, v il_ smod to 90% ls v gs t d_deadon = ls v gs fall to hs v gs rise, ls - comp trip value (~ 1 . 0 v g l) t o 1 0% hs v gs t pd_ s hglh = smod# rise to ls v gs rise, v ih_ smod to 10% ls v gs t d_deadoff = v sw h fall to ls v gs r i s e, s w - comp trip value (~ 2 . 2 v vs wh ) t o 1 0% ls v gs t pd_tsghh v sw h gh to v sw h gl t pd_phgl l t d_hold - off 90% l ess than t d_hold - off e x it 3 s t ate 1 .0v pwm v il_p w m v ih_p w m v tr i_hi v ih_p w m v ih_p w m 1 0% t r_gl t d_hold - off t pd_tsgl h l ess than t d_hold - off e x it 3 - state v ih p w m v tr i_hi v tr i_lo v il_p w m t pd_pl ghl t pd_tsghh dcm t f_gh t r_gh t d_ hold - off 1 0% ccm dcm ex it 3 - state 90% 1 0% 9 0% enter 3 - state enter 3 - state t d_deadoff t d_deadon enter 3 - state t f_gl v in v out 2.2v
www.onsemi.com 13 fdmf670 7b - extra - small high - performance, high - frequency drmos module skip mode ( s mod # ) the smod function allow s for higher c onverter efficiency under light - load conditions. during smod, the low - side fet gate signal is disa bled (held l ow ) , preventing dis charging of the output capacitors as the filter inductor current attempts reverse current flow ? also know n as ? d iode e mulation ? mode . when the smod # pin is pulled high , the synchronous buck converter w ork s in s ynchronous m o de . this mode allow s for gating on the low - side fet. when the smod # p in is pulled low , the low - side fet is gated off. if the smod # pin is connected to the pwm controller , the controller can actively enable or disable smod w hen the controller detects light - load condition from output current sensing. t his p in is a ctive l ow . see figure 26 for timing delays . table 2. smod # logic disb# pwm sm od# gh gl 0 x x 0 0 1 3 - s tate x 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 no t e : 4. the smod feature is intended to have low propagation delay betw een the smod signal and the low - side fet vgs response time to con tro l diode emulation on a cycle - by - cycle basis . figure 26. sm od # timing diagram t d_deadon pwm v sw h gh to v sw h gl t pd_phgll t pd_plghl t d_deadoff v ih_p w m v il_p w m 90% 1 0% 90% 1 . 0 v 2.2v t pd_phghh t pd_shglh delay from smod# going high to ls v gs high hs t urn - on with smod# low smod# t pd_slgll delay from smod# going l o w t o ls v gs low dcm ccm ccm 1 0% v ih_p w m 1 0% v out v ih_smod v il_smod 1 0%
www.onsemi.com 14 fdmf670 7b - extra - small high - performance, high - frequency drmos module application informa tion supply capacitor selection for the supply inputs (v drv & v cin ), a local ceramic bypass capaci tor is required to reduce noise and to supply peak transient current s during gate drive sw itching action . it is recommended to u se a minimum capacitor value of 1 f x7r or x5r. keep this capacitor close to the v cin and vdrv pins and connect it to the gnd plane w ith vias. bootstrap circuit the boo tstrap circuit uses a charge storage capacitor (c boot ), as show n in figure 27 . a boots trap capacitance of 100 nf x7r or x5r capacitor is typica lly adequate. a series bootstrap resistor may be needed for specific application s to improve sw itching noise immunity. the boot resistor may be required w hen operating near the maximum rated v in and is ef fective at controlling the high - sid e mosfet turn - on slew rate and v shw overshoot. typical r boot values from 0.5 to 2 .0 are effec tive in reducing v swh overshoot. vcin filter the v drv pin provides pow er to the gate drive of the high - side and low - side pow er mosfets. in most cases, vdrv can be connected directly to vcin, w hich supplies pow er to the logic circuitry of the gate driver. for additional noise immunity, an rc filter can be inserted betw een vdrv and vcin. recommended values w ould be 10 (r vcin ) placed betw een vdrv and vcin and 1f (c vcin ) f r om v cin to cgnd (see figure 28 ). pow er loss and efficiency measurement and calculation refer to figure 27 for pow er loss testing method. pow er loss calculations are : p in =(v in x i in ) + (v 5v x i 5 v ) (w) p sw =v sw x i out (w) p out =v out x i out (w) p loss_m odule =p in - p sw (w) p loss_board =p in - p ou t (w) eff module =100 x p sw /p in (%) eff board =100 x p out /p in (%) v 5 v disb pwm input off on c vdrv c vin c boot r boot l out c out a i 5 v a i in v in v v sw a i out fdmf 6707 b open - drain output vdrv vcin vin pwm thwn # boot vswh cgnd pgnd disb # phase smod # v out r vcin c vcin figure 27. power loss measurement block diagram v 5v disb pwm input off on c vdrv c vin c boot r boot l out c out a i 5v a i in v in v v sw a i out FDMF6707B open - drain output vdrv vcin vin pwm thwn# boot vswh cgnd pgnd disb# phase smod# r vcin c vcin v out figure 28. block diagram s how ing v cin f ilter
www.onsemi.com 15 fdmf670 7b - extra - small high - performance, high - frequency drmos module pcb layout guideline s figure 29 provides an example of a proper layout for the fdmf6 70 7b and criti cal components. all of the high - current paths, such as v in , v s wh , v out , and gnd copper, should be short and w ide for low inductance and resistance. this technique achiev es a more stable and evenly distributed current flow , along w ith enhanced heat radiation and system performance. the follow ing guidelines are recommendations for the pcb designer: 1. input ceramic bypass capacitors must be placed close t o the vin and pgnd pins. this help s reduce the high - current pow er loop inductance and the input current ripple induced by the p ow er mosfet sw itching operation. 2. the v swh copper trace serves tw o purposes . in addition to being the high - frequency current path from the dr mos package to the output inductor, it also serves as a heat sink for the low - side mosfet in the dr mos package. the trace should be short a nd w ide enough to present a low - impedance path for the high - frequency, high - current flow betw een the dr mos and inductor to minimize losse s and temperature rise. n ote that the vswh node is a high - voltage and high - frequency sw itching node w ith high noise potential. care should be taken to minimize coupling to adjacent traces. s ince th is copper trace also acts as a heat sink for the low er fet, balance using the largest area possible to improve dr mos cooling w hile maintaining acceptable noise emission. 3. an o utput inductor should be located close to the fdmf 6707b to minimize the pow er loss due to t he vswh copper trac e. c are should also be taken so the inductor dissipation does not heat the drmos. 4. pow ertrench? mosfets are used in the output stage. the p ow er mosfets are effective at minimiz ing ringing due to fast sw itching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the resistor and capacitor need to be of proper size for the pow er dissipation. 5. v cin, v drv , and boot capacitors should be placed as close as possible to the vcin to cgnd, vdrv to cgnd , and boot to phase pins to ensure clean and stable pow er. routing w idth and length should be considered as w ell. 6. inc l ude a trace from pha se to vswh to improve noise margin. keep the trace as short as possible. 7. the layout should inclu de a place holder to in sert a s ma ll - value series boot resistor (r boot ) betw een the boot c apacitor (c boot ) and dr mos boot pin. the boot - to - v sw h loop size, including r boot and c boot , should be as s mall as possible. the boot resistor may be required w hen operating near the maximum rated v in . the boot resistor is ef fective at controlling the high - side mosfet turn - on slew rate and vshw overshoot. r boot can improve noise operating margin in synchronous buck des igns that may have noise issues due to ground bounce or high positive and ne gative vswh ringing. how ever, i nserting a boot resistance low er s the dr mos efficiency. efficiency versus noise trade - offs must be considered. r boot values from 0.5 to 2.0 are typically effec tive in reducing vswh overshoot. 8. the v in and pgnd pins handle large current transients w ith freque ncy components greater than 100 mhz. if possible, these pins should be connected directly to the vin and board gnd planes. the u se of ther mal relief traces in series w ith these pins is discouraged since this adds inductance to the pow er path. a dded inductance in series w ith the vin or pgnd pin degrade s system noise immunity by increasing pos itive and negative vswh ringing . 9. cgnd pad and pgnd pins should be connected to the gnd plane copper w ith multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level betw een cgnd and pgnd. this could lead to faulty operation of the gate driver and mosfet s . 10. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add an additional boot to the pgnd capacitor : t his may lead to excess current flow through the boot diode. 11. the smod# and disb# pins have w eak internal p ull - up and pull - dow n current sources, respectively. these pins shoul d not have any noise filter capacitors . do not to float these pins unless absolutely necessary. 12. use multiple vias on each copper area to interconnect top, inner , and bottom layers to help distribute current flow and heat conduction. vias should be relatively large and of reasonabl y low inductance. critical high - frequency components , such as r boot , c boot , the rc snubber , and bypa ss capacitors should be located as close to the respective dr mo s module pins as possible on the top layer of the pcb. if this is not feasible, they should be connected from the ba ckside through a netw ork of low - inductance vias.
www.onsemi.com 16 fdmf670 7b - extra - small high - performance, high - frequency drmos module figure 29. pcb layout exam ple bottom view top v iew
www.onsemi.com 17 fdmf670 7b - extra - small high - performance, high - frequency drmos module physical dimensions bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo-220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) drawing file name: pqfn40arev3 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0.60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0.05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (40x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (40x) 4.400.10 0.10 c a b 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator may appear as optional 2.400.10 figure 30. 40- lead, clipbond pqfn dr mos, 6.0 x 6.0 m m package package drawings are provided as a service to customers considering o n semiconductor components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a n o n semiconductor r epresentative to verify or obtain the most recent revision. pa ckage sp ecifications do n ot expand the te rms o f o n semi con ductor ?s worldwide terms a nd co n d ition s, specifically the wa rra nty therein, which covers o n semi con ductor p roducts.
www.onsemi.com 18 fdmf670 7b - extra - small high - performance, high - frequency drmos module on semiconductor and the on semiconductor log o are trademarks of semiconductor components industries, llc dba on semiconducto r or its subsidiaries in the united states and/or oth er countries. on semiconductor owns the rig hts to a number of patents, tradema rks, cop yrig hts, trade secrets, and other intellectual property. a listing of on semiconductor?s product/patent coverag e ma y be accessed at www.onse mi.com/site/pdf/paten t - marking .pdf. on semiconductor reserves the rig ht to make chang es without further noti ce to an y prod ucts herein. on semiconductor makes no warrant y, representation or g uarantee reg arding the suitability of its p roducts for an y particular purpose, nor does on semiconductor assume a ny liability arising out of th e ap plication or use of an y pro duct or circuit, and specifically disclaims an y an d all liability, including without limitation special, conseq uential or incidental damag es. buyer is responsible for its products a nd applications using on semiconductor products, including compliance with all laws, reg ulations and safety req uirements or standards, reg ardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do var y in different applications and actual performance ma y vary o ver time. all operating parameters, including ?typicals? must be validated for each customer app lication b y customer?s technical e xperts. on semiconductor does not con vey an y license under its pa tent rig hts nor the rig hts of others. on semiconductor products are not desig ned, intended, or authorized for use as a critical component in life support systems or an y fda class 3 medical devices or medical devices with a same or simi lar classification in a foreig n jurisdiction or any de vices intended for implantation in the human bod y. should bu yer purchase or use on semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and h old on semiconductor and its officers , employees, subsidiaries, affiliates, and distributors harmless ag ainst all claims, costs, damag es, and exp enses, and reasonable att orney fe es arising out of, directly or indirectly, any claim of personal injury or d eath associated with such uninten ded or unauthorized use, even if such claim alleg es that on semiconductor was neglig ent reg arding the desig n or manufacture of the p art. on semiconductor is an eq ual opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303 - 675- 2175 or 800 - 344- 3860 toll free usa/canada fax : 303 - 675- 2176 or 800 - 344- 3867 toll free usa/canada email : orderlit@onsemi.com n. amer ic an technical support : 800 - 282- 9855 toll free usa/canada. eur ope, middle east and afr ica technical support : phone: 421 33 790 2910 japan customer focu s center phone: 81 - 3 - 5817- 1050 on semic onductor website : www.onsemi.com or der literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

▲Up To Search▲

Price & Availability of FDMF6707B

	To Download FDMF6707B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .